In association with an increase in the degree of integration of LSI chips, there has been a strong demand for a reduction in package size. Under the circumstances, various package structures have been proposed. In recent years, developments have been carried out intensively for stacking semiconductor bare chips through utilization of through-silicon vias formed therein. Meanwhile, dual-face packages of real chip size are also highly likely to be commercialized. Conventional dual-face packages of any technology require a through-silicon via structure (refer to Patent Documents 1 and 2). Since existing insulation methods for through holes in a semiconductor substrate involve high-temperature treatment, application of such the insulation methods to a semiconductor packaging process is difficult. Formation of through holes in a semiconductor substrate and insulation for the through holes still involve problems to be solved; therefore, wiring without need of through-silicon vias is desired.    Patent Document 1: Japanese Patent Application Laid-Open (kokai) No. 2003-249604    Patent Document 2: Japanese Patent Application Laid-Open (kokai) No. 2002-158312